NET(Z)TEST 
 the NET analyzing software to speed up your test process

Speed, Test Coverage and Fault Detection  

The Net(z)test method for all TAKAYA Flying Probe Testers (APT-8000- and APT-9000 series) records exactly the net properties of the tested modules and is therefore very different from standard test. The results are a considerable reduction in test time and an improvement of test coverage. This procedure systematically increases the probability of covering the fault types:

- SHORT
- OPEN
- Line Interrupt
- No Pin Contact

The standard test on the Flying Probe Tester includes the diode test and element test (R, L, C, D) and the short-circuit or SHORT test. With respect to the linear and non-linear characteristics of tested nets, several net types can be formed. The freedom from short-circuits of any net can be determined perfectly (method is patented) with the specific stimuli application of DC and AC stimuli sources of the tester. In the event of a short-circuit, at least one actual value on at least one of the nets involved is always outside the nominal range.

As already mentioned, the R-behavior (resistance), the L/C behavior (capacitance / inductance) and the D-behavior (diode/transistor) is tested on every net by the Net(z)Test. Therefore, in addition to the SHORT test between any two lines the following faults are detected: IC-Opens; when an IC-Pin/ Net or an internal resistance exists in the IC and internal impedance (for example a resistor) in the IC (decisive for increasing the fault coverage  in comparison with the standard solution) and all elements (R, L, C-D) connected to GND or VCC whose percentage is 50 to 90%. Outside the Net(z)Test only the potential free elements (no connection to potential) are tested.

We would like to highlight the improvements compared between the Net(z)Test and the standard test.

IC-Open test steps

In the standard test, only the faults detected by CC stimuli are recorded systematically (one IC on the network). In addition to this, the Net(z)Test also detects the open pins for ICs, which have a measurable internal impedance and are not well-known for generation tools (R, C). The debugging procedure for the network test records these values (as an alternative to the high ohm behavior).

SHORT - test

The Net(z)test concept has been specifically optimized for 100% fault coverage of SHORTs. The deviation in network properties in the event of a SHORT is detected by the effect of at least one type of stimulus. In contrast, the standard test only provides fault coverage for adjacent networks. The dependency of the fault coverage on the definition of "adjacent networks" also follows directly from this. Why does this step present problems for programs dealing with a greater number of modules (production test), in particular, and often result in a considerable loss of time in the test preparation phase? The answer is: the risk of redundant pin movements and unnecessarily long test times when the adjacent lines are defined too "generously" (radius/distance, for which a SHORT is realistically too big). However, eliminating this redundancy can result in reduced fault coverage. This question or decision-making problem - conditional on the coverage of all possible SHORTs - is not relevant for the Net(z)test.

Illustration: Fault coverage --- radius...
Listed below are some reasons that can bring about a significant increase in the number of SHORTs in "non-adjacent" networks:

1.) Modules with changes (additional wiring). 

2.) The small gaps between components on the component side are not recorded by the current module description, which means that the corresponding SHORT steps do not exist in the standard test.

3.) The description of the conductor path dimensions does not reflect the real conductor path area, so that the arithmetic distance between 2 networks is considerably greater than the actual distance. Result: missing SHORT test steps.

PIN CONTACT monitoring

A significant improvement on the standard test is the fact that at least one measurement is taken for each pin contact and a fault is reported in the event of bad pin contact. Naturally, the standard SHORT test steps cannot differentiate between good and bad contacts, which means that no contact monitoring is performed for most of the test steps. The introduction of the Net(z)test was therefore a significant step forward, particularly in relation to the production test.

LINE INTERRUPTS

The improvement compared to the standard test was achieved - as the table shows - by measuring the minimum network capacity values. Practical example: 500 modules with additional wiring (changes) were tested using APT8400. Of a total of 15 interrupts on the additional wires, 6 were detected using CC and CV stimulation. A further 8 interrupts were recorded with AC-stimuli (C < Cref). In this case, we can therefore establish an increase in the test coverage of 40% to around 94% for line interrupts.

PROGRAM GENERATION

For program generation it is nesessary to have CAD-Datas. At the moment the Net(z)Test software supports the FABMASTER and the UNICAM interfaces. With one of these tools it is very simple to generate a Net(z)Test program.

FAULT DETECTION

The Net(z)Test software tool for TAKAYA testers is based on standard programs generated previously (e.g. using FABMASTER- or UNICAM- paperless repair stations). The test steps that are not activated for the GO/NO GO test (but exist in the test program) can be activated as required in the event of a fault. The following procedure shows the steps that must be performed between the fault reporting and repair stage.

 
 



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